1. Field
Embodiments of the invention relate to non-volatile memory (NVM) devices. In particular, embodiments of the invention relate to NVM devices having floating gate field-effect transistors (FETs) with different source-gate and drain-gate border lengths.
2. Background Information
Various field-effect transistors (FETs) having floating gates, their properties, and their uses, are known in the arts. Two different examples of which are shown in FIGS. 1A-1B and FIGS. 2A-2B.
FIG. 1A is a cross-sectional side view of a prior art FET 100 having a floating gate 116. The FET includes a first doped region 108 in a substrate 106, and a second doped region 110 in the substrate. The first and the second doped regions define a channel region 112 of the substrate between them. A dielectric or other insulating layer 114 of the FET is over the channel region. The floating gate 116 is over the insulating layer. The floating gate 116 may be sufficiently insulated or isolated to store a charge thereon. Vertical sidewall spacers 118 are alongside the vertical sidewalls of the floating gate 116.
FIG. 1B is a top planar view of the prior art FET 100 of FIG. 1A. A section line labeled [FIG. 1A] is used to show the cross-sectional view of FIG. 1A. Notice that the border lengths (L0) between the floating gate and each of the doped regions are substantially equal. In practice, the border lengths may differ slightly due to manufacturing variability and/or imprecision, although the difference is typically less than 8%.
FETs having floating gates are commonly used as non-volatile memory (NVM) devices. In these applications, the floating gate may be used to store charge of an amount that encodes a value.
FIG. 2A is a cross-sectional side view of a prior art NVM device 201. The NVM device includes a first FET 200A and a second FET 200B. In this particular case the FETs are implemented as pFETs. An isolation region 204, such as shallow trench isolation (STI) separates and isolates the first and second FETs.
The first FET 200A includes a first doped region 208 and a second doped region 210 formed in an N-well 206 of a substrate 202. A channel region 212 of the substrate is defined between the first and second doped regions. An insulating layer 214 is over the channel region. A read/write floating gate 216 is over the insulating layer 214. Vertical sidewall spacers 218 are alongside the vertical sidewalls of the read/write floating gate 216.
Likewise, the second FET 200B includes a first doped region 228 and a second doped region 230 in an N-well 226 of the substrate 202. A channel region 232 of the substrate is defined between the first and second doped regions. An insulating layer 234 is over the channel region. A control gate 220 is over the insulating layer 214. Vertical sidewall spacers 238 are alongside the vertical sidewalls of the control gate 220.
FIG. 2B is a top planar view of the prior art pFET-based NVM device of FIG. 2A. A section line labeled [FIG. 2A] is used to show the cross-sectional view of FIG. 2A. Notice that read/write floating gate 216 and the control gate 220 are portions of a larger gate structure and are electrically coupled together. Notice also that the border lengths (L0) between the read/write floating gate 216 and each of the doped regions are substantially equal. In practice, the border lengths may differ slightly due to manufacturing variability and/or imprecision, although the difference is typically less than 8%. In the illustration, the read/write floating gate 216 and the control gate 220 have about the same size, although commonly the control gate may be larger than the read/write floating gate.
Device 201 operates as a memory as follows. A charge of an amount that encodes a value may be stored on the read/write floating gate 216. The read/write floating gate may be sufficiently insulated or isolated to retain the charge for a long time, as is desired for a memory.
In storing the charge on the read/write floating gate 216 in the first place, the control gate device 200B may be used to bias the read/write floating gate device 200A to allow the charge to be stored on the read/write floating gate 216. This may include controlling a voltage of the control gate 220 in order to control a voltage on the read/write floating gate 216. Electrons may be stored on the read/write floating gate 216 through an injection mechanism. The control gate 220 may be used to help turn on the read/write floating gate device 200A in order to store the charge. For example, the read/write floating gate device may be biased in such a way as to invert its channel region. Or the read/write floating gate device can be turned on in order to promote the electron injection onto the read/write floating gate 216. Accordingly, the control gate device 200B may facilitate storage of charge on the read/write floating gate.
However, the control gate 220 and the second FET 200B significantly increase the size of the overall NVM device 201. Elimination of the control gate and the second FET would allow for a smaller NVM device.
Elimination of the control gate may, however, make it difficult to store the charge of the amount that encodes the value on the floating gate. Without being able to separately control the voltage on the floating gate during such write operations, channel flow may be restricted which may tend to reduce the amount of charge that may be stored on the floating gate in a given amount of time.
FIG. 3A is a cross-sectional side view illustrating restriction of channel flow in a pFET-based NVM device 300, which omits a control gate. The pFET-based NVM device includes a P+ doped drain 308 and a P+ doped source 310 in a N-well 306 of a substrate 302. The device also includes a channel region 312, an insulating layer 314, a floating gate 316, and vertical sidewall spacers 318. The voltages of the source, drain, and N-well are capable of being controlled. However, the voltage of the floating gate 316 is not separately controlled, since the NVM device 300 lacks a control gate.
Charge may be stored on the floating gate 316 by impact ionized hot-electron injection (IHEI). The NVM device 300 may be turned on by biasing the source 310 and the N-well 306 to high voltages (e.g., pulling them high) and biasing the drain 308 to a low voltage (e.g., pulling it low). This may tend to promote flow of holes (h+) acting as charge carriers through the channel region 312 as shown.
However, as shown at comment 362, when the source 310 and the N-well 306 are biased to a high voltage, and the drain 308 is biased to a low voltage, then the floating gate 316 may tend to become capacitively coupled up to a high voltage, which in turn may restrict the intended flow of holes through the channel 312. This is because, at least conceptually, there are two sources of capacitance, i.e. from the source 310 and the N-well 306, that may pull the floating gate 316 up to a high voltage, whereas only one source of capacitance, i.e. from the drain 308, may pull the floating gate down to a low voltage. Accordingly, the two sources may dominate, and the voltage on the floating gate may increase.
For a pFET, imposing a high voltage on the floating gate may tend to turn the pFET off. As shown, a separation of charge may occur across the insulating layer 314, with holes (+) concentrated on the floating gate side and electrons (−) concentrated on the channel side. As shown by the “X” this may tend to restrict flow of the holes through the channel 312. This restriction of channel flow may limit the amount of charge that may be stored on the gate in a given amount of time.
FIG. 3B is a cross-sectional side view illustrating restriction of channel flow in an nFET-based NVM device 301, which omits a control gate. The pFET-based NVM device 301 includes an N+ doped drain 309 and an N+ doped source 311 in a P− substrate 303. The device also includes a channel region 313, an insulating layer 315, a floating gate 317, and vertical sidewall spacers 315. As before, the voltages of the source, drain, and N-well are capable of being controlled for operating device 301. However, the voltage of the floating gate 317 is not separately controlled, since the NVM device lacks a control gate.
Charge may be stored on the gate 317 of the nFET by channel hot-electron injection (CHEI). The NVM device may be turned on by biasing the source and the substrate to low voltage (e.g., pulling them low) and biasing the drain to a high voltage (e.g., pulling them high). This may tend to promote flow of electrons (e−) acting as charge carriers through the channel region.
However, as shown at comment 363, when the source and the substrate are biased to a low voltage and the drain is biased to a high voltage, then the floating gate may tend to be capacitively coupled down to a low voltage, which may restrict flow of electrons through the channel. For an nFET, imposing a low voltage on the floating gate may tend to turn the nFET off. As shown, a separation of charge may occur across the insulating layer, with electrons (−) concentrated on the floating gate side and holes (+) concentrated on the channel side. As shown by the “X” this may tend to restrict flow of the electrons (e−) through the channel. This restriction of channel flow may limit the amount of charge that may be stored on the gate in a given amount of time.